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As connected device implementations proliferate, the security of device data, communications and management is becoming an important focus for vendors and users. At the workstation and server level, robust security protocols within the Transmission Control Protocol/Internet Protocol (TCP/IP) family have been developed and deployed. However, traditional embedded implementations of security protocols have at least two serious shortcomings for use within low cost connected devices- the duplicate instances of complex cryptographic routines within each individual protocol implementation and the large performance overhead in executing these routines on lower power CPUs.
InterNiche CryptoEngine technology helps to ensure that no security compromises are required when adding networking within device implementations. CryptoEngine is a key technological component within the NicheStack family of portable device networking protocols, and is designed from the ground-up to optimize the support of cryptographic functions and available acceleration hardware across a range of security functions. By optimizing the modularity of cipher code within security protocols and authentication implementations, CryptoEngine enables implementations that are efficient in both memory and CPU usage. Device developers can also more easily and rapidly adapt to new algorithm requirements and take advantage of VLSI hardware that incorporates cipher acceleration engines.
CryptoEngine implements a pipelined architecture, providing synchronous and asynchronous encryption capabilities that have been proven as highly effective in optimizing overall device performance.
CryptoEngine can be used for protocol payload encryption and decryption within an application or for authentication of requests from other network nodes. Individual security algorithms can be transparently added, deleted, or re-implemented as required without changes to the overall code structure or applications. The modularity of CryptoEngine supports hardware and software cipher implementation for ease of code migration between platforms with differing capabilities, or benchmarking improvements in performance between architectures.
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